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EP4SGX230HF35C3N IC产品资料

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EP4SGX230HF35C3N IC产品资料
资料编号:
484265
资料标题:
EP4SGX230HF35C3N
品 牌:
ALTERA
点击次数:
123
文件大小:
11813
资料属性:
....

EP4SGX230HF35C3N 资料标题简介

Stratix IV Device Handbook, Volume 1

EP4SGX230HF35C3N 资料关键信息

Feature
The following list summarizes the features in the Stratix IV device family:
■ Up to 32 full-duplex CDR-based transceivers supporting data rates
between 600 Mbps and 8.5 Gbps. Up to 16 additional full-duplex
transceivers supporting data rates between 600 Mbps and 3.2 Gbps.
■ Dedicated circuitry to support physical layer functionality for
popular serial protocols, such as PCI Express (PIPE) Gen1 and Gen2,
Gigabit Ethernet, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF)
CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken ■ Complete PCI Express (PIPE) protocol solution with embedded PCI
Express hard IP blocks that implement PHY-MAC layer, Data Link
layer, and Transaction layer functionality
■ Programmable transmitter pre-emphasis and receiver equalization
circuitry to compensate for frequency-dependent losses in the
physical medium
■ Typical physical medium attachment (PMA) power consumption of
100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel
■ 72,600 to 681,100 equivalent logic elements (LEs) per device
■ 7,370 to 31,491 Kbits of enhanced TriMatrix memory consisting of
three RAM block sizes to implement true dual-port memory and
FIFO buffers
■ High-speed DSP blocks configurable as 9×9-bit, 12×12-bit, 18×18-bit,
and 36×36-bit full-precision multipliers at up to 540 MHz
■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132
periphery clocks (PCLK) per device
■ Programmable Power Technology that minimizes power while
maximizing device performance
■ Up to 1,104 user I/O pins arranged in 24 modular I/O banks that
support a wide range of single-ended and differential I/O standards
■ Support for high-speed external memory interfaces including DDR,
DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on
up to 24 modular I/O banks
■ High-speed LVDS I/O support with serializer/deserializer
(SERDES), dynamic phase alignment (DPA) and soft-CDR circuitry
at data rates up to 1.6 Gbps
■ Support for source-synchronous bus standards, including SGMII,
Gigabit Ethernet, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI,
UTOPIA IV, NPSI, and CSIX-L1
■ Pinouts for Stratix IV E devices designed to allow migration of
designs from Stratix III to Stratix IV E with minimal printed circuit
board impact

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EP4SGX230HF35C3N 相关资料推介

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